Index: include/nand_ids.h
===================================================================
--- include/nand_ids.h	(.../tags/at91bootstrap-1.14)	(revision 20)
+++ include/nand_ids.h	(.../branches/agama9263-1.14)	(revision 20)
@@ -43,6 +43,7 @@
 	{0x2cda, 0x800, 0x20000, 0x800, 0x40, 0x0, "MT29F2G08AAC\0"},
 	{0x20aa, 0x800, 0x20000, 0x800, 0x40, 0x0, "STMNAND02GR3B\0"},	
 	{0x2caa, 0x800, 0x20000, 0x800, 0x40, 0x0, "MT29F2G08ABD\0"},
+	{0x20da, 0x800, 0x20000, 0x800, 0x40, 0x0, "Numonyx NAND02GW3B2D 256Mb\0"},	
 	{0,}
 };
 
Index: include/debug.h
===================================================================
--- include/debug.h	(.../tags/at91bootstrap-1.14)	(revision 20)
+++ include/debug.h	(.../branches/agama9263-1.14)	(revision 20)
@@ -34,11 +34,14 @@
 #ifndef _DEBUG_H_
 #define _DEBUG_H_
 
+#if 0
 #define BAUDRATE(mck, baud) \
 	(((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
 	(mck / (baud * 16) + 1) : ((mck) / (baud * 16))
+#endif
 
 /* Global functions */
+extern unsigned int BAUDRATE(unsigned long mck, unsigned long baud);
 extern void dbg_init(unsigned int);
 extern void dbg_print(const char *ptr);
 
Index: main.c
===================================================================
--- main.c	(.../tags/at91bootstrap-1.14)	(revision 20)
+++ main.c	(.../branches/agama9263-1.14)	(revision 20)
@@ -37,6 +37,10 @@
 #include "include/nandflash.h"
 #include "include/norflash.h"
 
+#ifdef CFG_USER_PREJUMP_HANDLER
+extern void prejump_handler(void);
+#endif
+
 /*------------------------------------------------------------------------------*/
 /* Function Name       : main							*/
 /* Object              : Main function						*/
@@ -79,6 +83,10 @@
 	linux_arg(LINUX_ARG);	/* NOT IMPLEMENTED YET */
 #endif /* LINUX_ARG */
 
+#ifdef CFG_USER_PREJUMP_HANDLER
+	prejump_handler();
+#endif
+
 	/* Jump to the Image Address */
 	return JUMP_ADDR;
 }
Index: board/at91sam9263ek/nandflash/at91sam9263ek.h
===================================================================
--- board/at91sam9263ek/nandflash/at91sam9263ek.h	(.../tags/at91bootstrap-1.14)	(revision 20)
+++ board/at91sam9263ek/nandflash/at91sam9263ek.h	(.../branches/agama9263-1.14)	(revision 20)
@@ -113,7 +113,12 @@
 /* ******************************************************************* */
 /* Application Settings                                                */
 /* ******************************************************************* */
-#undef CFG_DEBUG
+#define CFG_DEBUG		1
+#define CFG_DEBUG_USART0	1
+#undef CFG_DEBUG_USART1
+#undef CFG_DEBUG_USART2
+#undef CFG_DEBUG_USART3
+
 #undef CFG_DATAFLASH
 
 #define CFG_NANDFLASH
Index: board/agama9263/agama9263.c
===================================================================
--- board/agama9263/agama9263.c	(.../tags/at91bootstrap-1.14)	(revision 0)
+++ board/agama9263/agama9263.c	(.../branches/agama9263-1.14)	(revision 20)
@@ -0,0 +1,213 @@
+/*
+ * Machine configuration for Agama9263 board
+ *
+ * derived from at91sam9263ek.c
+ * Copyright (c) 2006, Atmel Corporation
+
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "../../include/part.h"
+#include "../../include/gpio.h"
+#include "../../include/pmc.h"
+#include "../../include/debug.h"
+#include "../../include/sdramc.h"
+#include "../../include/main.h"
+#ifdef CFG_NANDFLASH
+#include "../../include/nandflash.h"
+#else
+#error "This machine only supports nandflash"
+#endif
+
+static inline unsigned int get_cp15(void)
+{
+	unsigned int value;
+	__asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value));
+	return value;
+}
+
+static inline void set_cp15(unsigned int value)
+{
+	__asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value));
+}
+
+
+#ifdef CFG_HW_INIT
+void hw_init(void)
+{
+	/* Configure PIOs */
+	const struct pio_desc hw_pio[] = {
+#ifdef CFG_DEBUG
+#if defined(CFG_DEBUG_USART0)
+		{"TXD", AT91C_PIN_PA(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"RXD", AT91C_PIN_PA(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
+#elif defined(CFG_DEBUG_USART1)
+		{"TXD", AT91C_PIN_PD(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"RXD", AT91C_PIN_PD(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
+#elif defined(CFG_DEBUG_USART2)
+		{"TXD", AT91C_PIN_PD(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"RXD", AT91C_PIN_PD(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
+#else
+		{"TXD", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"RXD", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
+#endif
+#endif
+		{"DS1", AT91C_PIN_PB(8),  0, PIO_DEFAULT, PIO_OUTPUT},
+		{"DS2", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_OUTPUT},
+		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+	};
+
+	/* Disable watchdog */
+	writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
+
+	/* At this stage the main oscillator is supposed to be enabled
+	 * PCK = MCK = MOSC */
+
+	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+	pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
+
+	/* PCK = PLLA = 2 * MCK */
+	pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
+	/* Switch MCK on PLLA output */
+	pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
+
+
+	/* Configure PLLB */
+	pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
+
+	/* Configure the PIO controller to output PCK0 */
+	pio_setup(hw_pio);
+	pio_set_value(AT91C_PIN_PB(8), 1);
+	pio_set_value(AT91C_PIN_PB(8), 0);
+	pio_set_value(AT91C_PIN_PB(8), 1);
+
+	/* Configure the EBI0 Slave Slot Cycle to 64 */
+	writel( (readl((AT91C_BASE_MATRIX + MATRIX_SCFG4)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG4));
+
+#ifdef CFG_DEBUG
+	/* Enable Debug messages on the DBGU */
+	dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
+	dbg_print("Start AT91Bootstrap...\n\r");
+#endif /* CFG_DEBUG */
+
+#ifdef CFG_SDRAM
+	/* Initialize the matrix */
+	/* VDDIOMSEL = 1 -> Memories are 3.3V powered */
+	writel(readl(AT91C_BASE_CCFG + CCFG_EBI0CSA) | (1 << 16) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBI0CSA);
+
+	/* Configure SDRAM Controller */
+	sdram_init(	AT91C_SDRAMC_NC_9  |
+				AT91C_SDRAMC_NR_12 |
+				AT91C_SDRAMC_CAS_2 |
+				AT91C_SDRAMC_NB_4_BANKS |
+				AT91C_SDRAMC_DBW_32_BITS |
+				AT91C_SDRAMC_TWR_2 |
+				AT91C_SDRAMC_TRC_7 |
+				AT91C_SDRAMC_TRP_2 |
+				AT91C_SDRAMC_TRCD_2 |
+				AT91C_SDRAMC_TRAS_5 |
+				AT91C_SDRAMC_TXSR_8,		/* Control Register       */
+				AT91C_SDRAMC_REFRESH,		/* Refresh Timer Register */
+				AT91C_SDRAMC_MD_SDRAM);		/* SDRAM (no low power)   */
+#endif	/* CFG_SDRAM */
+}
+#endif /* CFG_HW_INIT */
+
+
+#ifdef CFG_SDRAM
+void sdramc_hw_init(void)
+{
+	/* Configure PIOs */
+	const struct pio_desc sdramc_pio[] = {
+		{"D16", AT91C_PIN_PD(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D17", AT91C_PIN_PD(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D18", AT91C_PIN_PD(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D19", AT91C_PIN_PD(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D20", AT91C_PIN_PD(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D21", AT91C_PIN_PD(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D22", AT91C_PIN_PD(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D23", AT91C_PIN_PD(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D24", AT91C_PIN_PD(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D25", AT91C_PIN_PD(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D26", AT91C_PIN_PD(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D27", AT91C_PIN_PD(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D28", AT91C_PIN_PD(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D29", AT91C_PIN_PD(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D30", AT91C_PIN_PD(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D31", AT91C_PIN_PD(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+	};
+
+	/* Configure the SDRAMC PIO controller */
+	pio_setup(sdramc_pio);
+}
+#endif
+
+#ifdef CFG_NANDFLASH
+void nandflash_hw_init(void)
+{
+	/* Configure PIOs */
+	const struct pio_desc nand_pio[] = {
+		{"RDY_BSY", AT91C_PIN_PA(22), 0, PIO_PULLUP, PIO_INPUT},
+		{"NANDCS",  AT91C_PIN_PD(15), 0, PIO_PULLUP, PIO_OUTPUT},
+		{(char *) 0, 0, 0,  PIO_DEFAULT, PIO_PERIPH_A},
+	};
+
+	/* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
+	writel(readl(AT91C_BASE_CCFG + CCFG_EBI0CSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBI0CSA);
+		    
+	/* Configure SMC CS3 */
+ 	writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC0 + SMC_SETUP3);
+  	writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC0 + SMC_PULSE3);
+	writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE)						, AT91C_BASE_SMC0 + SMC_CYCLE3);
+	writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | 
+  		AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | AT91C_SM_TDF)						, AT91C_BASE_SMC0 + SMC_CTRL3);
+
+	/* Configure the PIO controller */
+	writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
+	writel((1 << AT91C_ID_PIOCDE), PMC_PCER + AT91C_BASE_PMC);
+
+	pio_setup(nand_pio);
+}
+
+void nandflash_cfg_16bits_dbw_init(void)
+{
+	writel(readl(AT91C_BASE_SMC0 + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC0 + SMC_CTRL3);
+}
+
+void nandflash_cfg_8bits_dbw_init(void)
+{
+	writel((readl(AT91C_BASE_SMC0 + SMC_CTRL3) & ~(AT91C_SMC_DBW)) | AT91C_SMC_DBW_WIDTH_EIGTH_BITS, AT91C_BASE_SMC0 + SMC_CTRL3);
+}
+
+#endif /* #ifdef CFG_NANDFLASH */
+
+#ifdef CFG_USER_PREJUMP_HANDLER
+void prejump_handler(void)
+{
+	pio_set_value(AT91C_PIN_PC(29), 1);
+	pio_set_value(AT91C_PIN_PC(29), 0);
+	pio_set_value(AT91C_PIN_PC(29), 1);
+}
+#endif
+
Index: board/agama9263/nandflash/at91sam9263ek.h
===================================================================
--- board/agama9263/nandflash/at91sam9263ek.h	(.../tags/at91bootstrap-1.14)	(revision 0)
+++ board/agama9263/nandflash/at91sam9263ek.h	(.../branches/agama9263-1.14)	(revision 20)
@@ -0,0 +1,136 @@
+/*
+ * Machine configuration for Agama9263 board
+ *
+ * derived from at91sam9263ek.h
+ * Copyright (c) 2006, Atmel Corporation
+
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AT91SAM9263EK_H
+#define _AT91SAM9263EK_H
+
+/*
+ * PMC Settings
+ */
+#ifdef CRYSTAL_16_36766MHZ
+	#define MASTER_CLOCK		(199919000/2)
+	#define PLL_LOCK_TIMEOUT	1000000
+	#define PLLA_SETTINGS		0x20AABF0E
+	#define PLLB_SETTINGS		0x10483F0E
+	#define AT91C_SDRAMC_REFRESH	((MASTER_CLOCK * 7) / 1000000)
+#endif
+
+#ifdef CRYSTAL_18_432MHZ
+	#define MASTER_CLOCK		(198656000/2)
+	#define PLL_LOCK_TIMEOUT	1000000
+	#define PLLA_SETTINGS		0x2060BF09
+	#define PLLB_SETTINGS		0x10483F0E
+	#define AT91C_SDRAMC_REFRESH	(1552)
+#endif
+
+/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
+#define MCKR_SETTINGS		(AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2)
+#define MCKR_CSS_SETTINGS	(AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS)
+
+/*
+ * NandFlash Settings
+ */
+#define AT91C_SMARTMEDIA_BASE	0x40000000
+
+#define AT91_SMART_MEDIA_ALE    (1 << 21)	/* our ALE is AD21 */
+#define AT91_SMART_MEDIA_CLE    (1 << 22)	/* our CLE is AD22 */
+
+#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOD_SODR = AT91C_PIO_PD15;} while(0)
+#define NAND_ENABLE_CE()  do { *(volatile unsigned int *)AT91C_PIOD_CODR = AT91C_PIO_PD15;} while(0)
+#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOA_PDSR & AT91C_PIO_PA22))
+
+/*
+ * SDRAMC Settings
+ */
+#ifdef CRYSTAL_16_36766MHZ
+	#define AT91C_SM_NWE_SETUP	(1 << 0)
+	#define AT91C_SM_NCS_WR_SETUP	(1 << 8)
+	#define AT91C_SM_NRD_SETUP	(1 << 16)
+	#define AT91C_SM_NCS_RD_SETUP	(1 << 24)
+  
+	#define AT91C_SM_NWE_PULSE 	(3 << 0)
+	#define AT91C_SM_NCS_WR_PULSE	(3 << 8)
+	#define AT91C_SM_NRD_PULSE	(3 << 16)
+	#define AT91C_SM_NCS_RD_PULSE	(3 << 24)
+  
+	#define AT91C_SM_NWE_CYCLE 	(5 << 0)
+	#define AT91C_SM_NRD_CYCLE	(5 << 16)
+
+	#define AT91C_SM_TDF	        (2 << 16)
+#endif
+
+#ifdef CRYSTAL_18_432MHZ
+	#define AT91C_BASE_SDRAMC 	AT91C_BASE_SDRAMC0
+	#define AT91C_EBI_SDRAM		AT91C_EBI0_SDRAM
+	#define AT91C_SM_NWE_SETUP	(1 << 0)
+	#define AT91C_SM_NCS_WR_SETUP	(0 << 8)
+	#define AT91C_SM_NRD_SETUP	(2 << 16)
+	#define AT91C_SM_NCS_RD_SETUP	(1 << 24)
+
+	#define AT91C_SM_NWE_PULSE 	(2 << 0)
+	#define AT91C_SM_NCS_WR_PULSE	(4 << 8)
+	#define AT91C_SM_NRD_PULSE	(4 << 16)
+	#define AT91C_SM_NCS_RD_PULSE	(5 << 24)
+
+	#define AT91C_SM_NRD_CYCLE	(6 << 16)
+	#define AT91C_SM_NWE_CYCLE 	(7 << 0)	/* 4 or 7 */
+
+	#define AT91C_SM_TDF	        (3 << 16)
+#endif
+
+/*
+ * Bootstrap Settings
+ */
+#define IMG_ADDRESS 	0x20000		/* Image Address in NandFlash */
+#define	IMG_SIZE	0x40000		/* Image Size in NandFlash    */
+
+#define MACH_TYPE       2381       	/* Agama9263 */
+#define JUMP_ADDR	0x23F00000	/* Final Jump Address 	      */
+
+/*
+ * Application Settings
+ */
+#define CFG_DEBUG		1
+#define CFG_DEBUG_USART0	1
+#undef CFG_DEBUG_USART1
+#undef CFG_DEBUG_USART2
+#undef CFG_DEBUG_USART3
+
+#define CFG_USER_PREJUMP_HANDLER	1
+
+#undef CFG_DATAFLASH
+
+#define CFG_NANDFLASH
+#undef	NANDFLASH_SMALL_BLOCKS	/* NANDFLASH_LARGE_BLOCKS used instead */
+
+#define CFG_HW_INIT
+#define CFG_SDRAM
+
+#endif
+
Index: board/agama9263/nandflash/Makefile
===================================================================
--- board/agama9263/nandflash/Makefile	(.../tags/at91bootstrap-1.14)	(revision 0)
+++ board/agama9263/nandflash/Makefile	(.../branches/agama9263-1.14)	(revision 20)
@@ -0,0 +1,112 @@
+CROSS_COMPILE=arm-angstrom-linux-gnueabi-
+TOOLCHAIN=gcc
+BOOTSTRAP_PATH=../../..
+
+# NandFlashBoot Configuration for Agama9263
+
+# Target name (case sensitive!!!)
+TARGET=AT91SAM9263
+# Board name (case sensitive!!!)
+BOARD=agama9263
+# Link Address and Top_of_Memory
+LINK_ADDR=0x300000
+TOP_OF_MEMORY=0x314000
+# Name of current directory
+PROJECT=nandflash
+
+CRYSTAL=CRYSTAL_18_432MHZ
+
+ifndef BOOT_NAME
+BOOT_NAME=$(PROJECT)_$(BOARD)
+endif
+
+INCL=./$(BOOTSTRAP_PATH)/board/$(BOARD)/$(PROJECT)
+
+ifeq ($(TOOLCHAIN), gcc)
+
+AS=$(CROSS_COMPILE)gcc
+CC=$(CROSS_COMPILE)gcc
+LD=$(CROSS_COMPILE)gcc
+NM= $(CROSS_COMPILE)nm
+SIZE=$(CROSS_COMPILE)size
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+CCFLAGS=-g -mcpu=arm9 -O0 -Wall -D$(TARGET) -D$(CRYSTAL) -I$(INCL)
+ASFLAGS=-g -mcpu=arm9 -c -Os -Wall -D$(TARGET) -D$(CRYSTAL) -I$(INCL) -DTOP_OF_MEM=$(TOP_OF_MEMORY)
+
+# Linker flags.
+#  -Wl,...:     tell GCC to pass this to linker.
+#    -Map:      create map file
+#    --cref:    add cross reference to map file
+LDFLAGS+=-nostartfiles -nostdlib  -Wl,-Map=$(BOOT_NAME).map,--cref
+LDFLAGS+=-T $(BOOTSTRAP_PATH)/elf32-littlearm.lds -Ttext $(LINK_ADDR)
+OBJS=crt0_gnu.o
+
+endif
+
+OBJS+=\
+	$(BOARD).o \
+	main.o \
+	gpio.o \
+	pmc.o \
+	debug.o \
+	sdramc.o \
+	nandflash.o \
+	_udivsi3.o \
+	_umodsi3.o \
+	div0.o \
+	udiv.o \
+	string.o
+
+rebuild: clean all
+
+all: 	$(BOOT_NAME)
+
+ifeq ($(TOOLCHAIN), gcc)
+$(BOOT_NAME): $(OBJS)
+	$(LD) $(LDFLAGS) -n -o $(BOOT_NAME).elf $(OBJS)
+	$(OBJCOPY) --strip-debug --strip-unneeded $(BOOT_NAME).elf -O binary $(BOOT_NAME).bin
+endif
+	
+	
+$(BOARD).o: $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c -o $(BOARD).o
+
+main.o: $(BOOTSTRAP_PATH)/main.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/main.c -o main.o
+
+gpio.o: $(BOOTSTRAP_PATH)/driver/gpio.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/gpio.c -o gpio.o
+
+pmc.o:  $(BOOTSTRAP_PATH)/driver/pmc.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/pmc.c -o pmc.o
+
+debug.o: $(BOOTSTRAP_PATH)/driver/debug.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/debug.c -o debug.o
+
+sdramc.o:  $(BOOTSTRAP_PATH)/driver/sdramc.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/sdramc.c -o sdramc.o
+
+nandflash.o:  $(BOOTSTRAP_PATH)/driver/nandflash.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/nandflash.c -o nandflash.o
+
+crt0_gnu.o:  $(BOOTSTRAP_PATH)/crt0_gnu.S
+	$(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/crt0_gnu.S -o crt0_gnu.o
+
+div0.o:  $(BOOTSTRAP_PATH)/lib/div0.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/div0.c -o div0.o
+
+string.o:  $(BOOTSTRAP_PATH)/lib/string.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/string.c -o string.o
+
+udiv.o:  $(BOOTSTRAP_PATH)/lib/udiv.c 
+	$(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/udiv.c -o udiv.o
+
+_udivsi3.o:  $(BOOTSTRAP_PATH)/lib/_udivsi3.S
+	$(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_udivsi3.S -o _udivsi3.o
+
+_umodsi3.o:  $(BOOTSTRAP_PATH)/lib/_umodsi3.S
+	$(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_umodsi3.S -o _umodsi3.o
+
+clean:
+	rm -f *.o *.bin *.elf *.map
Index: driver/debug.c
===================================================================
--- driver/debug.c	(.../tags/at91bootstrap-1.14)	(revision 20)
+++ driver/debug.c	(.../branches/agama9263-1.14)	(revision 20)
@@ -35,50 +35,77 @@
 
 #ifdef CFG_DEBUG
 
-/* Write DBGU register */
-static inline void write_dbgu(unsigned int offset, const unsigned int value)
+#if	defined(CFG_DEBUG_USART0)
+	#define USART_BASE	AT91C_BASE_US0
+	#define PERIPH_INIT()	do { writel((1 << AT91C_ID_US0), PMC_PCER + AT91C_BASE_PMC); } while(0);
+#elif	defined(CFG_DEBUG_USART1)
+	#define USART_BASE	AT91C_BASE_US1
+	#define PERIPH_INIT()	do { writel((1 << AT91C_ID_US1), PMC_PCER + AT91C_BASE_PMC); } while(0);
+#elif	defined(CFG_DEBUG_USART2)
+	#define USART_BASE	AT91C_BASE_US2
+	#define PERIPH_INIT()	do { writel((1 << AT91C_ID_US2), PMC_PCER + AT91C_BASE_PMC); } while(0);
+#else
+	#ifndef CFG_DEBUG_USART3
+		#define CFG_DEBUG_USART3
+	#endif
+	#define USART_BASE	AT91C_BASE_DBGU
+	#define PERIPH_INIT()	/* nada */
+#endif
+
+/* Write USART register */
+static inline void write_usart(unsigned int offset, const unsigned int value)
 {
-	writel(value, offset + AT91C_BASE_DBGU);
+	writel(value, offset + USART_BASE);
 }
 
-/* Read DBGU registers */
-static inline unsigned int read_dbgu( unsigned int offset)
+/* Read USART registers */
+static inline unsigned int read_usart(unsigned int offset)
 {
-	return readl(offset + AT91C_BASE_DBGU);
+	return readl(offset + USART_BASE);
 }
 
+unsigned int BAUDRATE(unsigned long mck, unsigned long baud)
+{
+	unsigned long divisor;
 
+	divisor = ((mck / 16) + (baud / 2)) / baud;
+
+	return (unsigned int)(divisor & 0xFFFF);
+}
+
 //*----------------------------------------------------------------------------
 //* \fn    dbg_init
-//* \brief This function is used to configure the DBGU COM port
+//* \brief This function is used to configure the USART COM port
 //*----------------------------------------------------------------------------*/
 void dbg_init(unsigned int baudrate)
 {
+	/* Configure the peripheral mux */
+	PERIPH_INIT();
 	/* Disable interrupts */
-	write_dbgu(US_IDR, -1);
+	write_usart(US_IDR, -1);
 	/* Reset the receiver and transmitter */
-	write_dbgu(US_CR, AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS  | AT91C_US_TXDIS);
+	write_usart(US_CR, AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS);
 	/* Configure the baudrate */
-	write_dbgu(US_BRGR, baudrate);
+	write_usart(US_BRGR, baudrate);
+	/* Enable RX and Tx */
+	write_usart(US_CR, AT91C_US_RXEN | AT91C_US_TXEN);
 	/* Configure USART in Asynchronous mode */
-	write_dbgu(US_MR, AT91C_US_PAR);
-	/* Enable RX and Tx */
-	write_dbgu(US_CR, AT91C_US_RXEN | AT91C_US_TXEN);
+	write_usart(US_MR, AT91C_US_CLKS_CLOCK | AT91C_US_CHMODE_NORMAL | AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_NBSTOP_1_BIT);
 }
 
-//*----------------------------------------------------------------------------
-//* \fn    dbg_print
-//* \brief This function is used to configure the DBGU
-//*----------------------------------------------------------------------------*/
-void dbg_print(const char *ptr)
+void dbg_putc(char c)
 {
-	int i=0;
+	if (c == '\n')
+		dbg_putc('\r');
 
-	while (ptr[i] != '\0') {
-		while ( !(read_dbgu(DBGU_CSR) & AT91C_US_TXRDY) );
-		write_dbgu(DBGU_THR, ptr[i]);
-		i++;
-	}
+	while ( !(read_usart(US_CSR) & AT91C_US_TXRDY) ) ;
+	write_usart(US_THR, c);
 }
 
+void dbg_print(const char *ptr)
+{
+	while (*ptr)
+		dbg_putc(*ptr++);
+}
+
 #endif /* CFG_DEBUG */
